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flash memory 1 k9f1208d0b k9f1208u0b k9f1208q0b advance document title 64m x 8 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 remark advance history initial issue. draft date apr. 24th 2004 note : for more detailed features and specifications including faq, please refer to samsung?s flash web site. http://www.samsung.com/products/semiconductor/flash/technicalinfo/datasheets.htm
flash memory 2 k9f1208d0b k9f1208u0b k9f1208q0b advance general description features voltage supply - 1.8v device(k9f1208q0b) : 1.70~1.95v - 2.65v device(k9f1208d0b) : 2.4~2.9v - 3.3v device(k9f1208u0b) : 2.7 ~ 3.6 v organization - memory cell array : (64m + 2048k)bit x 8 bit - data register : (512 + 16)bit x 8bit automatic program and erase - page program : (512 + 16)byte - block erase : (16k + 512)byte page read operation - page size : (512 + 16)byte - random access : 15 m s(max.) - serial page access : 50ns(min.) 64m x 8 bit nand flash memory fast write cycle time - program time : 200 m s(typ.) - block erase time : 2ms(typ.) command/address/data multiplexed i/o port hardware data protection - program/erase lockout during power transitions reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years command register operation intelligent copy-back unique id for copyright protection package - k9f1208x0b-ycb0/yib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - k9f1208x0b-gcb0/gib0 63- ball fbga (8.5 x 13 , 1.0 mm width) - k9f1208u0b-vcb0/vib0 48 - pin wsop i (12x17x0.7mm) - k9f1208x0b-pcb0/pib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch)- pb-free package - k9f1208x0b-jcb0/jib0 63- ball fbga - pb-free package - k9f1208u0b-fcb0/fib0 48 - pin wsop i (12x17x0.7mm)- pb-free package * k9f1208u0b-v,f(wsopi ) is the same device as k9f1208u0b-y,p(tsop1) except package type. offered in 64mx8bit the k9f1208x0b is 512m bit with spare 16m bit capacity. the device is offered in 1.8v, 2.65v, 3.3v vcc. i ts nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation can be perform ed in typical 200 m s on the 528-byte page and an erase operation can be performed in typical 2ms on a 16k-byte block. data in the page can be read out at 50ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as comma nd input. the on-chip write control automates all program and erase functions including pulse repetition, where required, and int ernal verification and margining of data. even the write-intensive systems can take advantage of the k9f1208x0b s extended reliability of 100k program/erase cycles by providing ecc(error correcting code) with real time mapping-out algorithm. the k9f1208x0b is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications req uiring non-volatility. product list part number vcc range pkg type k9f1208q0b-d,h 1.70 ~ 1.95v fbga K9F1208D0B-Y,p 2.4 ~ 2.9v tsop1 k9f1208d0b-d,h fbga k9f1208u0b-y,p 2.7 ~ 3.6v tsop1 k9f1208u0b-d,h fbga k9f1208u0b-v,f wsop1
flash memory 3 k9f1208d0b k9f1208u0b k9f1208q0b advance pin configuration (tsop1) k9f1208u0b-ycb0,pcb0/yib0,pib0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0 . 1 6 + 0 . 0 7 - 0 . 0 3 0 . 0 0 8 + 0 . 0 0 3 - 0 . 0 0 1 0 . 5 0 0 . 0 1 9 7 #48 #25 0 . 4 8 8 1 2 . 4 0 m a x 1 2 . 0 0 0 . 4 7 2 0 . 1 0 0 . 0 0 4 m a x 0 . 2 5 0 . 0 1 0 ( ) 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0 . 0 1 0 0 . 2 5 t y p 0 . 1 2 5 + 0 . 0 7 5 0 . 0 3 5 0 . 0 0 5 + 0 . 0 0 3 - 0 . 0 0 1 0.50 0.020 ( ) 0 . 2 0 + 0 . 0 7 - 0 . 0 3
flash memory 4 k9f1208d0b k9f1208u0b k9f1208q0b advance k9f1208x0b-dcb0,hcb0/dib0,hib0 r/b /we /ce vss ale /wp /re cle nc nc nc nc vcc nc nc i/o0 i/o1 nc nc vccq i/o5 i/o7 vss i/o6 i/o4 i/o3 i/o2 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c pin configuration (fbga) 3 4 5 6 1 2 a b c d g e f h top view
package dimensions flash memory 5 8.50 0.10 #a1 side view top view 63-ball fbga (measured in millimeters) 0 . 9 0 0 . 1 0 0.45 0.05 4 3 2 1 a b c d g bottom view 1 3 . 0 0 0 . 1 0 63- ? 0.45 0.05 0 . 8 0 x 7 = 5 . 6 0 1 3 . 0 0 0 . 1 0 0.80 x 5= 4.00 0.80 0 . 3 5 0 . 0 5 0.10max b a 2 . 8 0 2.00 8.50 0.10 (datum b) (datum a) 0.20 m a b ? 0 . 8 0 0 . 8 0 x 1 1 = 8 . 8 0 0.80 x 9= 7.20 6 5 13.00 0.10 e f h #a1 index mark(optional)
flash memory 6 k9f1208d0b k9f1208u0b k9f1208q0b advance pin configuration (wsop1) k9f1208u0b-vcb0,fcb0/vib0,fib0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c dnu n.c n.c n.c r/b re ce dnu n.c vcc vss n.c dnu cle ale we wp n.c n.c dnu n.c n.c n.c n.c dnu n.c i/o7 i/o6 i/o5 i/o4 n.c dnu n.c vcc vss n.c dnu n.c i/o3 i/o2 i/o1 i/o0 n.c dnu n.c n.c package dimensions 48-pin lead plastic very very thin small out-line package type (i) 48 - wsop1 - 1217f unit :mm 15.40 0.10 #1 #24 0 . 2 0 + 0 . 0 7 - 0 . 0 3 0 . 1 6 + 0 . 0 7 - 0 . 0 3 0 . 5 0 t y p ( 0 . 5 0 0 . 0 6 ) #48 #25 0 . 1 0 + 0 . 0 7 5 - 0 . 0 3 5 17.00 0.20 0 ~ 8 0.45~0.75 1 2 . 0 0 0 . 1 0 0.58 0.04 0.70 max (0.01min) 1 2 . 4 0 m a x
flash memory 7 k9f1208d0b k9f1208u0b k9f1208q0b advance pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 (k9f1208x0b) data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. regarding ce control during read operation, refer to ?page read? section of device operation . re read enable the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r/ b ready/busy output the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. vcc q output buffer power vcc q is the power supply for output buffer. vcc q is internally connected to vcc, thus should be biased to vcc. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. dnu do not use leave it disconnected.
flash memory 8 k9f1208d0b k9f1208u0b k9f1208q0b advance 512byte 16 byte figure 1-1. k9f1208x0b functional block diagram figure 2-1. k9f1208x0b array organization v cc x-buffers 512m + 16m bit command nand flash array (512 + 16)byte x 131072 y-gating page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 25 a 0 - a 7 command ce re we wp i/0 0 i/0 7 v cc/ v ccq v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 128k pages (=4,096 blocks) 512 byte 8 bit 16 byte 1 block =32 pages = (16k + 512) byte i/o 0 ~ i/o 7 1 page = 528 byte 1 block = 528 byte x 32 pages = (16k + 512) byte 1 device = 528bytes x 32pages x 4096 blocks = 528 mbits column address row address (page address) page register cle ale note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * l must be set to "low". * the device ignores any additional input of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 a 24 4th cycle a 25 *l *l *l *l *l *l *l
flash memory 9 k9f1208d0b k9f1208u0b k9f1208q0b advance product introduction the k9f1208x0b is a 528mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. spare sixteen columns are located from column address of 512 to 527. a 528-byte data register is connected to memory cell arrays accommodating data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected to form a nand structure. each of the 16 cells resides in a different page. a block consists o f two nand structured strings. a nand structure consists of 16 cells. total 135168 nand cells reside in a block. the array organizatio n is shown in figure 2. the program and read operations are executed on a page basis, while the erase operation is executed on a bloc k basis. the memory array consists of 4,096 separately erasable 16k-byte blocks. it indicates that the bit by bit erase operation is pro- hibited on the k9f1208x0b. the k9f1208x0b has addresses multiplexed into 8 i/o's. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. command, address and data are all written through i/o's b y bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. the 64m byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row address, in tha t order. page read and page program need the same four address cycles following the required command input. in block erase oper- ation, however, only the three row address cycles are used. device operations are selected by writing specific commands into the command register. table 1 defines the specific commands of the k9f1208x0b. the device provides simultaneous program/erase capability up to four pages/blocks. by dividing the memory array into four 128mbi t separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4x while still maintaini ng the conventional 512 byte structure. the extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block ou t of selected multiple pages/blocks. usage of multi-plane operations will be described further throughout this document. in addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to anoth er of the same plane without the need for transporting the data to and from the external buffer memory. since the time-consuming bu rst- reading and data-input cycles are removed, system performance for solid-state disk application is significantly increased. the device includes one block sized otp(one time programmable), which can be used to increase system security or to provide identification capabilities. detailed information can be obtained by contact with samsung. table 1. command sets note : 1. the 00h command defines starting address of the 1st half of registers. the 01h command defines starting address of the 2nd half of registers. after data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. 2. page program(true) and copy-back program(true) are available on 1 plane operation. page program(dummy) and copy-back program(dummy) are available on the 2nd,3rd,4th plane of multi plane operation . 3. the 71h command should be used for read status of multi plane operation. caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st. cycle 2nd. cycle 3rd. cycle acceptable command during busy read 1 00h/01h (1) - - read 2 50h - - read id 90h - - reset ffh - - o page program (true) (2) 80h 10h - page program (dummy) (2) 80h 11h - copy-back program(true) (2) 00h 8ah 10h copy-back program(dummy) (2) 03h 8ah 11h block erase 60h d0h - multi-plane block erase 60h----60h d0h - read status 70h - - o read multi-plane status 71h (3) - - o
flash memory 10 k9f1208d0b k9f1208u0b k9f1208q0b advance the device is arranged in four 128mbit memory planes. each plane contains 1,024 blocks and 528 byte page registers. this allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. the block address map is configured so that multi-plane program/erase operations can be executed for every four sequential blocks. plane 0 plane 1 plane 2 plane 3 (1024 block) (1024 block) (1024 block) (1024 block) page 0 page 1 page 31 page 30 memory map block 0 page 0 page 1 page 31 page 30 block 1 page 0 page 1 page 31 page 30 block 2 page 0 page 1 page 31 page 30 block 3 page 0 page 1 page 31 page 30 block 4 page 0 page 1 page 31 page 30 block 5 page 0 page 1 page 31 page 30 block 6 page 0 page 1 page 31 page 30 block 7 page 0 page 1 page 31 page 30 block 4088 page 0 page 1 page 31 page 30 block 4089 page 0 page 1 page 31 page 30 block 4090 page 0 page 1 page 31 page 30 block 4091 page 0 page 1 page 31 page 30 block 4092 page 0 page 1 page 31 page 30 block 4093 page 0 page 1 page 31 page 30 block 4094 page 0 page 1 page 31 page 30 block 4095 528byte page registers figure 3. memory array map 528byte page registers 528byte page registers 528byte page registers
flash memory 11 k9f1208d0b k9f1208u0b k9f1208q0b advance recommended operating conditions (voltage reference to gnd, k9f1208x0b-xcb0 : t a =0 to 70 c, k9f1208x0b-xib0 : t a =-40 to 85 c) parameter symbol k9f1208q0b(1.8v) k9f1208d0b(2.65v) k9f1208u0b(3.3v) unit min typ. max min typ. max min typ. max supply voltage v cc 1.70 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 v supply voltage v ccq 1.70 1.8 1.95 2.4 2.65 2.9 2.7 3.3 3.6 v supply voltage v ss 0 0 0 0 0 0 0 0 0 v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc, +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit 1.8v device 3.3v/2.65v device voltage on any pin relative to v ss v in/out -0.6 to + 2.45 -0.6 to + 4.6 v v cc -0.2 to + 2.45 -0.6 to + 4.6 v ccq -0.2 to + 2.45 -0.6 to + 4.6 temperature under bias k9f1208x0b-xcb0 t bias -10 to +125 c k9f1208x0b-xib0 -40 to +125 storage temperature k9f1208x0b-xcb0 t stg -65 to +150 c k9f1208x0b-xib0 short circuit current ios 5 ma
flash memory 12 k9f1208d0b k9f1208u0b k9f1208q0b advance dc and operating characteristics (recommended operating conditions otherwise noted.) note : vil can undershoot to -0.4v and vih can overshoot to vcc +0.4v for durations of 20 ns or less. parameter symbol test conditions k9f1208x0b unit 1.8v 2.65v 3.3v min typ max min typ max min typ max operating current sequential read i cc 1 trc=50ns, ce =v il i out =0ma - 8 15 - 10 20 - 10 20 ma program i cc 2 - - 8 15 - 10 20 - 10 20 erase i cc 3 - - 8 15 - 10 20 - 10 20 stand-by current(ttl) i sb 1 ce =v ih , wp =0v/v cc - - 1 - - 1 - - 1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =0v/v cc - 10 50 - 10 50 - 10 50 m a input leakage current i li v in =0 to vcc(max) - - 10 - - 10 - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 - - 10 - - 10 input high voltage v ih* i/o pins v ccq -0.4 - v ccq +0.3 v ccq -0.4 - v ccq +0.3 2.0 - v ccq +0.3 v except i/o pins v cc -0.4 - v cc +0.3 v cc -0.4 - v cc +0.3 2.0 - v cc +0.3 input low voltage, all inputs v il* - -0.3 - 0.4 -0.3 - 0.5 -0.3 - 0.8 output high voltage level v oh k9f1208q0b :i oh =-100 m a k9f1208d0b :i oh =-100 m a k9f1208u0b :i oh =-400 m a v ccq -0.1 - - v ccq -0.4 - - 2.4 - - output low voltage level v ol k9f1208q0b :i ol =100ua k9f1208d0b :i ol =100 m a k9f1208u0b :i ol =2.1ma - - 0.1 - - 0.4 - - 0.4 output low current(r/ b ) i ol (r/ b ) k9f1208q0b :v ol =0.1v k9f1208d0b :v ol =0.1v k9f1208u0b :v ol =0.4v 3 4 - 3 4 - 8 10 - ma
flash memory 13 k9f1208d0b k9f1208u0b k9f1208q0b advance capacitance ( t a =25 c, v cc =1.8v/2.65v/3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the device may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid bloc ks is pre- sented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits . do not erase or program factory-marked bad blocks . refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require error correction up to 1k program/erase cycles. 3. minimum 1004 valid blocks are guaranteed for each contiguous 128mb memory space. parameter symbol min typ. max unit valid block number n vb 4,026 - 4,096 blocks ac test condition (k9f1208x0b-xcb0 :ta=0 to 70 c, k9f1208x0b-xib0:ta=-40 to 85 c k9f1208q0b : vcc=1.70v~1.95v , k9f1208d0b : vcc=2.4v~2.9v , k9f1208u0b : vcc=2.7v~3.6v unless otherwise noted) parameter k9f1208q0b k9f1208d0b k9f1208u0b input pulse levels 0v to vcc q 0v to vcc q 0.4v to 2.4v input rise and fall times 5ns 5ns 5ns input and output timing levels vcc q /2 vcc q /2 1.5v k9f1208q0b:output load (vcc q :1.8v +/-10%) k9f1208d0b:output load (vcc q :2.65v +/-10%) k9f1208u0b:output load (vcc q :3.0v +/-10%) 1 ttl gate and cl=30pf 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf k9f1208u0b:output load (vcc q :3.3v +/-10%) - - 1 ttl gate and cl=100pf mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode h l l h x read mode command input l h l h x address input(4clock) h l l h h write mode command input l h l h h address input(4clock) l l l h h data input l l l h x data output l l l h h x during read(busy) on k9f1208x0b-y,p or k9f1208u0b-v,f x x x x h x during read(busy) on the devices except k9f1208x0b-y,p and k9f1208u0b-v,f x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by
flash memory 14 k9f1208d0b k9f1208u0b k9f1208q0b advance ac timing characteristics for command / address / data input note : 1. if tcs is set less than 10ns, twp must be minimum 35ns, otherwise, twp may be minimum 25ns. parameter symbol min max unit cle setup time t cls 0 0 0 - - - ns cle hold time t clh 10 10 10 - - - ns ce setup time t cs 0 0 0 - - - ns ce hold time t ch 10 10 10 - - - ns we pulse width t wp 25 25 (1) 25 (1) - - - ns ale setup time t als 0 0 0 - - - ns ale hold time t alh 10 10 10 - - - ns data setup time t ds 20 20 20 - - - ns data hold time t dh 10 10 10 - - - ns write cycle time t wc 45 45 45 - - - ns we high hold time t wh 15 15 15 - - - ns program / erase characteristics parameter symbol min typ max unit program time t prog - 200 500 m s dummy busy time for multi plane program t dbsy 1 10 m s number of partial program cycles in the same page main array nop - - 1 cycle spare array - - 2 cycles block erase time t bers - 2 3 ms
flash memory 15 k9f1208d0b k9f1208u0b k9f1208q0b advance ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. 2. to break the sequential read cycle, ce must be held high for longer time than tceh. 3. the time to ready depends on the value of the pull-up resistor tied r/ b pin. parameter symbol min max unit k9f1208q0b k9f1208d0b k9f1208u0b k9f1208q0b k9f1208d0b k9f1208u0b data transfer from cell to register t r - - - 15 15 15 m s ale to re delay t ar 10 10 10 - - - ns cle to re delay t clr 10 10 10 - - - ns ready to re low t rr 20 20 20 - - - ns re pulse width t rp 25 25 25 - - - ns we high to busy t wb - - - 100 100 100 ns read cycle time t rc 50 50 50 - - - ns re access time t rea - - - 35 30 30 ns ce access time t cea - - - 45 45 45 ns re high to output hi-z t rhz - - - 30 30 30 ns ce high to output hi-z t chz - - - 20 20 20 ns re or ce high to output hold t oh 15 15 15 - - - ns re high hold time t reh 15 15 15 - - - ns output hi-z to re low t ir 0 0 0 - - - ns we high to re low t whr 60 60 60 - - - ns device resetting time(read/pro- t rst - - - 5/10/500 (1) 5/10/500 (1) 5/10/500 (1) m s parameter symbol min max unit k9f1208u0b- y,v,p,f only last re high to busy(at sequential read) t rb - 100 ns ce high to ready(in case of interception by ce at read) t cry - 50 +tr(r/ b ) (3) ns ce high hold time(at the last serial read) (2) t ceh 100 - ns
flash memory 16 k9f1208d0b k9f1208u0b k9f1208q0b advance nand flash technical notes identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nfor- mation regarding the invalid block(s) is so called as the invalid block information. devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the perf or- mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system d esign must be able to mask out the invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is guara n- teed to be a valid block, does not require error correction up to 1k program/erase cycles. all device locations are erased(ffh) except locations where the invalid block(s) information is written prior to shipping. the i nvalid block(s) status is defined by the 6th byte(x8 device) or 1st word(x16 device) in the spare area. samsung makes sure that either the 1st or 2nd page of every invalid block has non-ffh(x8 device) or non-ffffh(x16 device) data at the column address of 517(x8 device) or 256 and 261(x16 device). since the invalid block information is also erasable in most cases, it is impossible to rec over the information once it has been erased. therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(figure 4). any intentional e rasure of the original invalid block information is prohibited. * check "ffh" at the column address figure 4. flow chart to create invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table of the 1st and 2nd page in the block 517(x8 device) or 256 and 261(x16 device)
flash memory 17 k9f1208d0b k9f1208u0b k9f1208q0b advance nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? write 00h i/o 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h read status register write address wait for tr time verify data no program completed or r/b = 1 ? program error yes no yes * program error yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation within its life time, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for th e actual data.the following possible failure modes should be considered to implement a highly reliable system. in the case of status read fail- ure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. to improve the efficiency of mem- ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement or ecc correction read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
flash memory 18 k9f1208d0b k9f1208u0b k9f1208q0b advance erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) block replacement * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4 do not further erase block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { ~ 1st (n-1)th nth (page) { ~ an error occurs.
flash memory 19 k9f1208d0b k9f1208u0b k9f1208q0b advance samsung nand flash has three address pointer commands as a substitute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255byte), ?01h? command sets the pointer to ?b? area(256~511byte), and ?50h? command sets the pointer to ?c? area(512~527byte). with these commands, the starting column address can be set to any of a whole page(0~527byte). ?00h? or ?50h? is sustained until another address pointer command is inputted. ?01h? command, however, is effec tive only for one operation. after any operation of read, program, erase, reset, power_up is executed once with ?01h? command, the address pointer returns to ?a? area by itself. to program data starting from ?a? or ?c? area, ?00h? or ?50h? command must be inp utted before ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. to program data starting fro m ?b? area, ?01h? command must be inputted right before ?80h? command is written. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 01h (2) command input sequence for programming ?b? area address / data input 80h 10h 01h 80h 10h address / data input ?b?, ?c? area can be programmed. it depends on how many data are inputted. ?01h? command must be rewritten before every program operation the address pointer is set to ?b? area(256~51 1 ), and will be reset to ?a? area after every program operation is executed. 50h (3) command input sequence for programming ?c? area address / data input 80h 10h 50h 80h 10h address / data input only ?c? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?c? area(512~527), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b?,?c? area can be programmed. pointer operation of k9f1208x0b(x8) table 2. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) "a" area 256 byte (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 5. block diagram of pointer operation
flash memory 20 k9f1208d0b k9f1208u0b k9f1208q0b advance system interface using ce don?t-care. ce we t wp t ch t cs start add.(4cycle) 80h data input ce cle ale we i/o x data input ce don?t-care ? ? 10h for an easier system interface, ce may be inactive during the data-loading or sequential data-reading as shown below. the internal 528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. in addition , for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce during the data-loading and reading would provide significant savings in power consumption. start add.(4cycle) 00h ce cle ale we i/o x data output(sequential) ce don?t-care ? r/ b t r re t cea out t rea ce re i/o x figure 7. program operation with ce don?t-care. figure 8. read operation with ce don?t-care. on k9f1208u0b-y,p or k9f1208u0b-v,f ce must be held low during tr
flash memory 21 k9f1208d0b k9f1208u0b k9f1208q0b advance command latch cycle ce we cle ale i/o x command address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh device i/o data i/ox data in/out k9f1208x0b(x8 device) i/o 0 ~ i/o 7 ~528byte ce we cle ale i/o x a0~a7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t alh t ds t dh t wp a9~a16 a17~a24 a25
flash memory 22 k9f1208d0b k9f1208u0b k9f1208q0b advance input data latch cycle ce cle we din 0 din 1 din n ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp serial access cycle after read (cle=l, we =h, ale=l) re ce r/ b dout dout dout t rc t rea t rr t oh t rea t reh t rea t oh t rhz* ? ? ? ? ? ? ? notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. i/ox i/ox t chz* t rhz*
flash memory 23 k9f1208d0b k9f1208u0b k9f1208q0b advance t chz t oh status read cycle ce we cle re i/o x 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir t oh t oh t whr t cea t cls read1 operation (read one page) x8 device : m = 528 , read cmd = 00h or 01h x16 device : m = 264 , read cmd = 00h 1) notes : 1) is only valid on k9f1208u0b-y,p or k9f1208u0b-v,f on k9f1208u0b-y,p or k9f1208u0b-v,f ce must be held low during tr 1) ce cle r/ b i/o x we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 column address page(row) address t wb t ar t r t rc t rhz t rr dout m t rb t cry t wc ? ? ? a 25 t ceh 1) n address t chz t rhz t oh ? ? ? ? ? ? ? ?
flash memory 24 k9f1208d0b k9f1208u0b k9f1208q0b advance on k9f1208u0b-y,p or k9f1208u0b-v,f ce must be held low during tr on k9f1208u0b-y,p or k9f1208u0b-v,f ce must be held low during tr read1 operation (intercepted by ce ) ce cle r/ b i/o x we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 page(row) address address column t wb t ar t chz t r t rr t rc read2 operation (read one page) ce cle r/ b i/o x we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n+m m address n+m t ar t r t wb t rr a 0 ~a 3 : valid address a 4 ~a 7 : don t care ? ? a 25 a 25 selected row start address m 512 16 t oh ? ? ? ? ? ? ? ?
flash memory 25 k9f1208d0b k9f1208u0b k9f1208q0b advance page program operation ce cle r/ b i/o x we ale re 80h 70h i/o 0 din n din 10h 527 a 0 ~ a 7 a 17 ~ a 24 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc sequential row read operation (within a block) ce cle r/ b i/o x we ale re 00h a 0 ~ a 7 busy m output a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout 527 dout 0 dout 1 dout 527 busy m+1 output n ready ? ? ? ? ? ? a 25 ? ? ? a 25 ? ? ? ? ? ? ? ? ? ? ?
flash memory 26 k9f1208d0b k9f1208u0b k9f1208q0b advance block erase operation (erase one block) ce cle r/ b i/o x we ale re 60h a 17 ~ a 24 a 9 ~ a 16 auto block erase setup command erase command read status command i/o 0 =1 error in erase doh 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase page(row) address t wc a 25
flash memory 27 k9f1208d0b k9f1208u0b k9f1208q0b advance m u l t i - p l a n e p a g e p r o g r a m o p e r a t i o n c e c l e r / b i / o x w e a l e r e 8 0 h d i n n d i n 1 1 h m a 0 ~ a 7 a 1 7 ~ a 2 4 a 9 ~ a 1 6 s e q u e n t i a l d a t a i n p u t c o m m a n d c o l u m n a d d r e s s p a g e ( r o w ) a d d r e s s 1 u p t o 5 2 8 b y t e d a t a s e r i a l i n p u t p r o g r a m m a x . t h r e e t i m e s r e p e a t a b l e t d b s y t w b t w c ? ? ? a 2 5 ? c o m m a n d l a s t p l a n e i n p u t & p r o g r a m t d b s y : t y p . 1 u s m a x . 1 0 u s ( d u m m y ) d i n n d i n 1 0 h 5 2 7 a 0 ~ a 7 a 1 7 ~ a 2 4 a 9 ~ a 1 6 t p r o g t w b ? ? ? a 2 5 ? i / o 8 0 h a 0 ~ a 7 & a 9 ~ a 2 5 i / o 0 ~ 7 r / b 5 2 8 b y t e d a t a a d d r e s s & d a t a i n p u t 1 1 h 8 0 h a d d r e s s & d a t a i n p u t 1 1 h 8 0 h a d d r e s s & d a t a i n p u t 1 1 h 8 0 h a d d r e s s & d a t a i n p u t 1 0 h e x . ) f o u r - p l a n e p a g e p r o g r a m t d b s y t d b s y t d b s y t p r o g p r o g r a m c o n f i r m c o m m a n d ( t r u e ) 8 0 h 7 1 h 7 1 h r e a d m u l t i - p l a n e s t a t u s c o m m a n d a 0 ~ a 7 & a 9 ~ a 2 5 5 2 8 b y t e d a t a a 0 ~ a 7 & a 9 ~ a 2 5 5 2 8 b y t e d a t a a 0 ~ a 7 & a 9 ~ a 2 5 5 2 8 b y t e d a t a ? ? ? ? ? ? ? ? ? ? ? ? ? ?
flash memory 28 k9f1208d0b k9f1208u0b k9f1208q0b advance multi-plane block erase operation block erase setup command erase confirm command read multi-plane statuscommand max. 4 times repeatable 60h a 9 ~ a 25 i/o 0 ~ 7 r/ b address 60h a 9 ~ a 25 60h a 9 ~ a 25 60h a 9 ~ a 25 d0h 71h t bers * for multi - plane erase operation, block address to be erased should be repeated before "d 0 h" command. ex.) four-plane block erase operation ce cle r/ b i/o x we ale re 60h a 17 ~ a 24 a 9 ~ a 16 doh 71h i/o 0 busy t wb t bers page(row) address t wc a 25
flash memory 29 k9f1208d0b k9f1208u0b k9f1208q0b advance read id operation ce cle i/o x we ale re 90h read id command maker code 00h ech device t rea address. 1cycle a5h c0h multi plane code id defintition table 90 id : access command = 90h description 1 st byte 2 nd byte 3 rd byte 4 th byte maker code device code must be don?t -cared supports multi plane operation device device code k9f1208q0b 36h k9f1208d0b 76h k9f1208u0b 76h code
flash memory 30 k9f1208d0b k9f1208u0b k9f1208q0b advance copy-back program operation ce cle r/ b i/o x we ale re 00h 70h i/o 0 8ah a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc a 0 ~a 7 a 17 ~a 24 a 9 ~a 16 column address page(row) address busy t wb t r ? a 25 a 25 10h copy-back data input command on k9f1208u0b-y,p or k9f1208u0b-v,f ce must be held low during tr busy ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
flash memory 31 k9f1208d0b k9f1208u0b k9f1208q0b advance device operation page read upon initial device power up, the device defaults to read1 mode. this operation is also initiated by writing 00h to the command regis- ter along with four address cycles. once the command is latched, it does not need to be written for the following page read oper ation. three types of operations are available : random read, serial page read and sequential row read. the random read mode is enabled when the page address is changed. the 528 bytes of data within the selected page are transferred to the data registers in less than 15 m s (t r ). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/ b pin. ce must be held low while in busy for k9f1208u0b-yxb0 or k9f1208u0b-vxb0, while ce is don?t-care with k9f1208x0b-gxb0 or k9f1208x0b-jxb0. if ce goes high before the device returns to ready, the random read operation is inter- rupted and busy returns to ready as the defined by tcry. since the operation was aborted, the serial page read does not output v alid data. once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data stating from the selected column address up to the last column address. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of 512 to 527 bytes may be selectively accessed by writing the read2 command. addresses a 0 to a 3 set the starting address of the spare area while addresses a 4 to a 7 are ignored. the read1 command(00h/01h) is needed to move the pointer back to the main area. fig- ures 7 to 10 show typical sequence and timings for each read operation. sequential row read is available only on k9f1208x0b-y,p or k9f1208u0b-v,f : after the data of last column address is clocked out, the next page is automatically selected for sequential row read. waiting 15 m s again allows reading the selected page. the sequential row read operation is terminated by bringing ce high. unless the operation is aborted, the page address is automatically incremented for sequential row read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the sequential read 1 and 2 operation is allowed only within a block and after the last pa ge of a block is readout, the sequential read operation must be terminated by bringing ce high. when the page address moves onto the next block, read command and address must be given. figures 9, 10 show typical sequence and timings for sequential row read operation.
flash memory 32 k9f1208d0b k9f1208u0b k9f1208q0b advance figure 7. read1 operation start add.(4cycle) 00h data output(sequential) ce cle ale r/ b we i/o 0 ~ 7 re t r on k9f1208u0b-y,p or k9f1208u0b-v,f ce must be held low during tr a 0 ~ a 7 & a 9 ~ a 25 (00h command) data field spare field main array (01h command) data field spare field 1st half array 2st half array note : 1) after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 01h command is only available on x8 device(k9f1208x0b). 1)
flash memory 33 k9f1208d0b k9f1208u0b k9f1208q0b advance figure 8. read2 operation 50h data output(sequential) spare field ce cle ale r/ b we start add.(4cycle) i/o x re figure 9. sequential row read1 operation (only for k9f1208u0b-y,p and k9f1208u0b-v,f valid within a block) 00h 01h a 0 ~ a 7 & a 9 ~ a 25 i/o x r/ b start add.(4cycle) data output data output data output 1st 2nd nth (528 byte) (528 byte) t r t r t r t r the sequential read 1 and 2 operation is allowed only within a block and after the last page of a block is read- out, the sequential read operation must be terminated by bringing ce high. when the page address moves onto the next block, read command and address must be given. ? ( 00h command) data field spare field ( 01h command) data field spare field 1st half array 2nd half array 1st 2nd nth 1st half array 2nd half array 1st 2nd nth block on k9f1208u0b-y,p or k9f1208u0b-v,f ce must be held low during tr main array data field spare field a 0 ~ a 7 & a 9 ~ a 25
flash memory 34 k9f1208d0b k9f1208u0b k9f1208q0b advance figure 10. sequential row read2 operation (only for k9f1208u0b-y,p and k9f1208u0b-v,f valid within a block) page program the device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 bytes, in a single page program cycle. the number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. the addressing may be done i n any random order in a block. a page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the approp ri- ate cell. serial data loading can be started from 2nd half array by moving pointer. about the pointer operation, please refer to the attached technical notes. the serial data loading period begins by inputting the serial data input command(80h), followed by the four cycle address input and then serial data loading. the bytes other than those to be programmed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate the pro- gramming process. the internal write state control automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/ b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit(i/o 0) may be checked(figure 11) . the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remain s in read status command mode until another valid command is written to the command register. 50h a 0 ~ a 3 & a 9 ~ a 25 i/o x r/ b start add.(4cycle) data output data output data output 2nd nth (16byte) (16byte) 1st figure 11. program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 25 i/o 0 ~ 7 r/ b address & data input i/o 0 pass 528 byte data 10h 70h fail t r t r t r t prog ? data field spare field 1st block (a 4 ~ a 7 : don ?t care) nth
flash memory 35 k9f1208d0b k9f1208u0b k9f1208q0b advance figure 12. block erase operation block erase the erase operation is done on a block(16k byte) basis. block address loading is accomplished in three cycles initiated by an er ase setup command(60h). only address a 14 to a 25 is valid while a 9 to a 13 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bit(i/o 0) may be checked. figure 12 details the sequence. 60h block add. : a 14 ~ a 25 i/o x r/ b address input(3cycle) i/o 0 pass d0h 70h fail t bers multi-plane page program multi-plane page program is an extension of page program, which is executed for a single plane with 528 byte page registers. sin ce the device is equipped with four memory planes, activating the four sets of 528 byte page registers enables a simultaneous progr am- ming of four pages. partial activation of four planes is also permitted. after writing the first set of data up to 528 byte into the selected page register, dummy page program command (11h) instead of actual page program (10h) is inputted to finish data-loading of the current plane and move to the next plane. since no programmi ng process is involved, r/ b remains in busy state for a short period of time(tdbsy). read status command (standard 70h or alternate 71h) may be issued to find out when the device returns to ready state by polling the ready/busy status bit(i/o 6). then the next set of data for one of the other planes is inputted with the same command and address sequences. after inputting data for the last p lane, actual true page program (10h) instead of dummy page program command (11h) must be followed to start the programming pro- cess. the operation of r/ b and read status is the same as that of page program. since maximum four pages are programmed simultaneously, pass/fail status is available for each page when the program operation completes. the extended status bits (i/o1 through i/o 4) are checked by inputting the read multi-plane status register. status bit of i/o 0 is set to "1" when any of the pages fails. multi-plane page program with "01h" pointer is not supported, thus prohibited. figure 13. four-plane page program 80h 11h 80h 11h 80h 11h 80h 10h data input plane 0 plane 1 plane 2 plane 3 (1024 block) (1024 block) (1024 block) (1024 block) block 0 block 4 block 4092 block 4088 block 1 block 5 block 4093 block 4089 block 2 block 6 block 4094 block 4090 block 3 block 7 block 4095 block 4091 80h a 0 ~ a 7 & a 9 ~ a 25 i/o x r/ b 528 bytes address & data input 11h 80h address & data input 11h 80h address & data input 11h 80h address & data input 10h t dbsy t dbsy t dbsy t prog 71h
flash memory 36 k9f1208d0b k9f1208u0b k9f1208q0b advance restriction in addressing with multi plane page program while any block in each plane may be addressable for multi-plane page program, the five least significant addresses(a9-a13) for the selected pages at one operation must be the same. figure 14 shows an example where 2nd page of each addressed block is selected for four planes. however, any arbitrary sequence is allowed in addressing multiple planes as shown in figure15. 80h plane 2 11h 80h 11h 80h 11h 80h 10h plane 0 plane3 plane 1 plane 0 plane 1 plane 2 plane 3 (1024 block) (1024 block) (1024 block) (1024 block) page 0 page 1 page 31 page 30 block 0 page 0 page 1 page 31 page 30 block 1 page 0 page 1 page 31 page 30 block 2 page 0 page 1 page 31 page 30 block 3 figure 16. multi-plane page program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 25 i/o 0 ~ 7 r/ b address & data input i/o pass 10h 71h fail t prog last plane input multi-plane block erase basic concept of multi-plane block erase operation is identical to that of multi-plane page program. up to four blocks, one from each plane can be simultaneously erased. standard block erase command sequences (block erase setup command followed by three address cycles) may be repeated up to four times for erasing up to four blocks. only one block should be selected from each plan e. the erase confirm command initiates the actual erasing process. the completion is detected by analyzing r/ b pin or ready/busy status (i/o 6). upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(i/o 1 through i/o 4). figure 17. four block erase operation 60h a 0 ~ a 7 & a 9 ~ a 25 i/o x r/ b address 60h 60h 60h d0h 71h i/o pass fail t bers (3 cycle) address (3 cycle) address (3 cycle) address (3 cycle) figure 14. multi-plane program & read status operation figure 15. addressing multiple planes 528 bytes
flash memory 37 k9f1208d0b k9f1208u0b k9f1208q0b advance copy-back program figure 18. one page copy-back program operation 00h a 0 ~ a 7 & a 9 ~ a 25 i/o x r/ b add.(4cycles) i/o 0 pass 8ah 70h fail t prog a 0 ~ a 7 & a 9 ~ a 25 add.(4cycles) t r source address destination address the copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. the benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. the operation for performing a copy-back program is a sequent ial execution of page-read without burst-reading cycle and copying-program with the address of destination page. a normal read opera - tion with "00h" command and the address of the source page moves the whole 528byte data into the internal page registers. as soo n as the device returns to ready state, page-copy data-input command (8ah) with the address cycles of destination page followed may be written. the program confirm command (10h) is required to actually begin the programming operation. copy-back program operation is allowed only within the same memory plane. once the copy-back program is finished, any additional partial page pro- gramming into the copied pages is prohibited before erase. a14 and a15 must be the same between source and target page. figure18 shows the command sequence for single plane operation. "when there is a program-failure at copy-back operation, error is reported by pass/fail status. but if the soure page has a bit error for charge loss, accumulated copy-back operations could also accumulate bit errors. for this reason, two bit ecc is recommended for copy-back operation." 10h
flash memory 38 k9f1208d0b k9f1208u0b k9f1208q0b advance multi-plane copy-back program multi-plane copy-back program is an extension of one page copy-back program into four plane operation. since the device is equipped with four memory planes, activating the four sets of 528 bytes page registers enables a simultaneous multi-plane copy- back programming of four pages. partial activation of four planes is also permitted. first, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal page buffers. any further read operation for transferring the addressed pages to the corresponding page register must be execute d with "03h" command instead of "00h" command. any plane may be selected without regard to "00h" or "03h". up to four planes may be addressed. data moved into the internal page registers are loaded into the destination plane addresses. after the input of co m- mand sequences for reading the source pages, the same procedure as multi-plane page programming except for a replacement address command with "8ah" is executed. since no programming process is involved during data loading at the destination plane address , r/ b remains in busy state for a short period of time(tdbsy). read status command (standard 70h or alternate 71h) may be issued to find out when the device returns to ready state by polling the ready/busy status bit(i/o 6). after inputting data for the last plane, actual true page program (10h) instead of dummy page program command (11h) must be followed to start the programming process. the operation of r/ b and read status is the same as that of page program. since maximum four pages are programmed simultaneously, pass/fail status is available for each page when the program operation completes. no pointer operation is suppor ted with multi-plane copy-back program. once the multi-plane copy-back program is finished, any additional partial page pro- gramming into the copied pages is prohibited before erase once the multi-plane copy-back program is finished. figure 19. four-plane copy-back program 8ah 11h 8ah 11h 8ah 11h 8ah 10h destination plane 0 plane 1 plane 2 plane 3 (1024 block) (1024 block) (1024 block) (1024 block) block 0 block 4 block 4092 block 4088 block 1 block 5 block 4093 block 4089 block 2 block 6 block 4094 block 4090 block 3 block 7 block 4095 block 4091 00h 03h 03h 03h source plane 0 plane 1 plane 2 plane 3 (1024 block) (1024 block) (1024 block) (1024 block) block 4 block 4092 block 4088 block 5 block 4093 block 2 block 6 block 4094 block 4090 block 3 block 7 block 4095 block 4091 address address input input block 0 block 1 block 4089 block 4089 max three times repeatable max three times repeatable
flash memory 39 k9f1208d0b k9f1208u0b k9f1208q0b advance 0 0 h a 0 ~ a 7 & a 9 ~ a 2 5 i / o x r / b s o u r c e a d d r e s s a d d . ( 4 c y c . ) 0 3 h f i g u r e 2 0 . f o u r - p l a n e c o p y - b a c k p a g e p r o g r a m ( c o n t i n u e d ) t r t d b s y a 0 ~ a 7 & a 9 ~ a 2 5 d e s t i n a t i o n a d d r e s s a d d . ( 4 c y c . ) 1 1 h 7 1 h a 0 ~ a 7 & a 9 ~ a 2 5 s o u r c e a d d r e s s a d d . ( 4 c y c . ) 8 a h 0 3 h a 0 ~ a 7 & a 9 ~ a 2 5 s o u r c e a d d r e s s a d d . ( 4 c y c . ) ? ? a 0 ~ a 7 & a 9 ~ a 2 5 d e s t i n a t i o n a d d r e s s a d d . ( 4 c y c . ) 1 1 h 8 a h a 0 ~ a 7 & a 9 ~ a 2 5 d e s t i n a t i o n a d d r e s s a d d . ( 4 c y c . ) 1 0 h 8 a h t r t p r o g t d b s y m a x . 4 t i m e s ( 4 c y c l e s o u r c e a d d r e s s i n p u t ) r e p e a t a b l e m a x . 4 t i m e s ( 4 c y c l e d e s t i n a t i o n a d d r e s s i n p u t ) r e p e a t a b l e t r : n o r m a l r e a d b u s y t d b s y : t y p i c a l 1 u s , m a x 1 0 u s ? ? ? ? t r
flash memory 40 k9f1208d0b k9f1208u0b k9f1208q0b advance read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle output s the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 4 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, a read command(00h or 50h) should be given before sequential page read cycle. for read status of multi plane program/erase, the read multi-plane status command(71h) should be used to find out whether multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. the pass/fail status data must be checked only in the ready condition after the completion of multi-plane program or erase operation . table4. read staus register definition note : 1. i/o 0 describes combined pass/fail condition for all planes. if any of the selected multiple pages/blocks fails in program/ erase operation, it sets "fail" flag. 2. the pass/fail status applies only to the corresponding plane. i/o no. status definition by 70h command definition by 71h command i/o 0 total pass/fail pass : "0" fail : "1" pass : "0" (1) fail : "1" i/o 1 plane 0 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 2 plane 1 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 3 plane 2 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 4 plane 3 pass/fail must be don?t -cared pass : "0" (2) fail : "1" i/o 5 reserved must be don?t -cared must be don?t-cared i/o 6 device operation busy : "0" ready : "1" busy : "0" ready : "1" i/o 7 write protect protected : "0" not protected : "1" protected : "0" not protected : "1"
flash memory 41 k9f1208d0b k9f1208u0b k9f1208q0b advance read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. four read cycles sequentially output the manufacture code(ech), and the device code, reserved(a5h), multi plane operation code(c0h) respectively. a5h must be don?t-cared. c0h means that device supports multi plane operation. the command register remains in read id mode until further commands are issued to it. figure 21 shows the operation sequence. figure 21. read id operation 1 ce cle i/o 0 ~ 7 ale re we 90h 00h ech address. 1cycle maker code device code t cea t ar t rea device a5h c0h multi-plane code t whr code device device code k9f1208q0b 36h k9f1208d0b 76h k9f1208u0b 76h
flash memory 42 k9f1208d0b k9f1208u0b k9f1208q0b advance figure 22. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 5 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/ b pin transitions to low for trst after the reset command is written. refer to figure 22 below. table5. device status after power-up after reset operation mode read 1 waiting for next command ffh i/o 0 ~ 7 r/ b t rst
flash memory 43 k9f1208d0b k9f1208u0b k9f1208q0b advance ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr(r/ b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 23). its value c an be determined by the following guidance. v cc r/ b open drain output device gnd rp figure 23. rp vs tr ,tf & rp vs ibusy ibusy busy ready vcc voh tf tr vol 1.8v device - v ol : 0.1v, v oh : vcc q -0.1v 3.3v device - v ol : 0.4v, v oh : 2.4v c l 2.65v device - v ol : 0.4v, v oh : vcc q -0.4v
flash memory 44 k9f1208d0b k9f1208u0b k9f1208q0b advance t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 100pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 100 tf 200 300 400 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + s i l = 1.85v 3ma + s i l where i l is the sum of the input currents of all devices tied to the r/ b pin. rp value guidance rp(max) is determined by maximum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + s i l = 3.2v 8ma + s i l t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 1.7 1.7 1.7 1.7 1.7 0.85 0.57 0.43 rp(min, 2.65v part) = v cc (max.) - v ol (max.) i ol + s i l = 2.5v 3ma + s i l t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr @ vcc = 2.65v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 2.3 2.3 2.3 2.3 2.3 1.1 0.75 0. 5 5
flash memory 45 k9f1208d0b k9f1208u0b k9f1208q0b advance the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 1.1v(1.8v device), 1.8v(2.65v device), 2v(3.3v device). wp pin provides hard- ware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 10 m s is required before internal circuit gets ready for any command sequences as shown in figure 24. the two step command sequence for program/erase provides additional software protection. figure 24. ac waveforms for power transition v cc wp high ? ? we data protection & power-up sequence 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v 10 m s ? ? 2.65v device : ~ 2.0v 2.65v device : ~ 2.0v

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